View HSD8M64D4B-10_632825.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HANBit
HSD8M64D4B
Synchronous DRAM Module 64Mbyte (8Mx64-Bit), DIMM, 4Banks, 4K Ref., 3.3V Part No. HSD8M64D4B
GENERAL DESCRIPTION
The HSD8M64D4B is a 8M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 2M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M64D4B is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification
HSD8M64D4B-10 HSD8M64D4B- 13 * Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * JEDEC standard * All inputs are sampled at the positive going edge of the system clock * The used device is2Mx16Bitx4Banks SDRAM : 100MHz ( CL=2) : 133MHz ( CL=3) HSD8M64D4B-10L : 100MHz ( CL=3)
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
1
HANBit
PIN ASSIGNMENT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC Vss NC NC Vcc /WE DQM0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol DQM1 /CS0 DU Vss A0 A2 A4 A6 A8 A10 BA1 Vcc Vcc CLK0 Vss NC /CS2 DQM2 DQM3 NC Vcc NC NC NC NC Vss DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol DQ18 DQ19 Vcc DQ20 NC NC CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss CLK2 NC WP SDA SCL Vcc PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Symbol Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC Vss NC NC Vcc /CAS DQM4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
HSD8M64D4B
Symbol DQM5 NC /RAS Vss A1 A3 A5 A7 A9 BA0 A11 Vcc CLK1 NC Vss CKE0 NC DQM6 DQM7 NC Vcc NC NC NC NC Vss DQ48 DQ49
PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol DQ50 DQ51 Vcc DQ52 NC NC NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss CLK3 NC SA0 SA1 SA2 Vcc
PIN NAMES
Pin Name A0 ~ A11 DQ0 ~ DQ63 CKE0 ~CKE1 /RAS /WE Vcc SDA DU Function Address input (Multiplexed) Data input/output Clock enable input Row address strobe Write enable Power supply (3.3V) Serial data I/O Do t use Pin Name BA0 ~ BA1 CLK0 ~ CLK3 CS0 /CAS DQM0 ~ 7 Vss SCL NC Function Select bank Clock input Chip select input Column address strobe DQM Ground Serial clock No connection
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
2
HANBit
FUNCTIONAL BLOCK DIAGRAM
HSD8M64D4B
DQ0-63
CKE0
/CAS
CKE CAS RAS CE CKE CAS RAS WE
U1
CLK DQ0-15 DQM0
CLKA DQM0 DQM1
/RAS
/CS0
A0-A11 BA0-1 DQM1 CLK DQ16-31 DQM2
U2
WE A0-A11 BA0-1
/CS2
CE CKE CAS RAS CE
DQM3 CLK DQ32-47 DQM4
DQM2 DQM3 CLKC DQM4 DQM5
U3
WE A0-A11 BA0-1
DQM5
CKE CAS RAS CE
U4
WE A0-A11 BA0-1
CLK DQ48-63 DQM6 DQM7
DQM6 DQM7
/WE A0 - A11 BA0-1
Vcc
Two 0.1uF Capacitors per each SDRAM
Vss
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
3
HANBit
PIN FUNCTION DESCRIPTION
Pin CLK /CE Name System clock Chip enable CLK, CKE and DQM Input Function
HSD8M64D4B
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. CKE Clock enable Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. A0 ~ A11 Address Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. BA0 ~ BA1 Bank select address Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. /RAS Row address strobe Enables row access & precharge. Column address /CAS strobe /WE Write enable Latches data in starting from CAS, WE active. Data input/output DQM0 ~ 7 mask DQ0 ~ 63 Vcc/Vss supply/ground Data input/output Power Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Makes data output Hi-Z, tSHZ after the clock and masks the output. Enables column access. Enables write operation and row precharge. Latches column addresses on the positive going edge of the CLK with CAS low.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature
SYMBOL VIN ,OUT Vcc PD TSTG
RATING -1V to 4.6V -1V to 4.6V 4W -55oC to 150oC
Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
4
HANBit
DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4
HSD8M64D4B
UNIT V V V V V
NOTE
1 2 IOH = -2mA IOL = 2mA 3
Input leakage current I IL -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Clock /RAS, /CAS,/WE,/CS, CKE, L(U)DQM Address DQ (DQ0 ~ DQ15) SYMBOL CCLK CIN CADD COUT MIN 2.5 2.5 2.5 5 MAX 4.0 5.0 5.0 6.5 UNITS pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current (One bank active) ICC1 tRC tRC(min) IO = 0mA ICC2P CKE VIL(max) tCC=10ns CKE & CLK ( VIL(max) ICC2PS 4 tCC=( CKE ( VIH(min) Precharge standby current in ICC2N non power-down mode CS* VIH(min), tCC=10ns 80 mA mA 4 mA 600 560 560 mA 1 13 10 10L VERSION UNIT NOTE
Precharge standby current in power-down mode
Input signals are changed one time during 20ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
5
HANBit
CKE VIH(min) ICC2NS CLK VIL(max), tCC= 28
HSD8M64D4B
Input signals are stable Active standby current in ICC3P ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), CS*(VIH(min), Active standby current in non power-down mode (One bank active) ICC3NS ICC3N tCC=10ns 120 Input signals are changed one time during 20ns CKE(VIH(min) CLK (VIL(max), tCC=( 80 mA 20 mA 20
power-down mode
Input signals are stable IO = 0 mA Operating current ICC4 (Burst mode) 4Banks Activated tCCD = 2CLKs Refresh current Self refresh current Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. ICC5 ICC6 tRC tRC(min) CKE 0.2V 880 840 6 840 mA mA 2 Page burst 720 580 580 mA 1
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
6
HANBit
+3.3V
HSD8M64D4B
Vtt=1.4V 1200 DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA DOUT Z0=50 50pF 50
(Fig. 1) DC output load
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time SYMBOL -13 tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
UNIT -10 20 20 20 50 100 65 70 2 1 1 1 2 ea 70 -10L 20 20 20 50 ns ns ns ns ns ns CLK CLK CLK CLK 15 20 20 45
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data
1 2 2 2 3 4
tRDL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
7
HANBit
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -13 PARAMETER CLK cycle time CAS 7.5 latency=3 tCC CAS 10 latency=2 CLK to valid output delay CAS 5.4 latency=3 tSAC CAS latency=2 Output data hold time CAS 2.7 latency=3 tOH CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS 5.4 latency=3 tSHZ CAS latency=2 6 7 6 6 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 3 3 2 1 1 3 3 2 1 1 3 3 3 6 7 6 6 10 12 1000 1000 1000 10 10 SYMBOL MIN MAX MIN MAX MIN MAX -10 -10L
HSD8M64D4B
UNIT
NOTE
ns
1
ns
1,2
ns
2
ns ns ns ns ns ns
3 3 3 3 3 2
ns
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
8
HANBit
HSD8M64D4B
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode register set Auto refresh Refresh Self refres h Auto disable Auto disable Auto disable Auto disable Burst Stop Precharg e Bank selection All banks Entry Exit Entry Exit H H H L H L H H X H L X X L H L H L L H L X H L H L L L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X X V X X X 7 V X L H X precharge precharge H X L H L L X V H X X precharge Entry Exit CKE n-1 H H L H CKE N X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1 A10/ AP OP code X X Row address L H X L H L H X V H Column Address (A0 ~ A7) Column L Address (A0 ~ A7) 4,5 6 4 4,5 4 A11 A9~A0 NOTE 1,2 3 3 3 3
Bank active & row addr. Read & column address precharge
Write & column address
Clock suspend or active power down
Precharge down mode DQM
power
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
9
HANBit
HSD8M64D4B
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
PACKAGING INFORMATION
Unit : Inch(mm)
2.54 mm MAX 0.25 mm MAX
1.27 mm
Gold: 1.04 0.10 mm Solder: 0.914 0.10 mm 28.250.15
1.27 0.08 mm
(Solder & Gold Plating)
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
10
HANBit
HSD8M64D4B
ORDERING INFORMATION
Part Number
Density
Org.
Package 168 Pin DIMM 168 Pin DIMM 168 Pin DIMM
Ref.
Vcc
MAX.frq 133MHz (CL=3) 100MHz (CL=2) 100MHz (CL=3)
HSD8M64D4B-13 HSD8M64D4B-10 HSD8M64D4B-10L
64MByte 64MByte 64MByte
x 64 x 64 x 64
4K 4K 4K
3.3V 3.3V 3.3V
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
11

▲Up To Search▲

Price & Availability of HSD8M64D4B-10

	To Download HSD8M64D4B-10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .